Sub-Block Oriented Media Processor Architecture

Sub-block oriented media processor architecture is presented. A block oriented instruction set extension is proposed to process and transfer 1D or 2D data blocks. Two programmable processors are employed to perform sequential processing and block oriented processing respectively. We evaluated the performance potential of the media processor architecture using a special FPGA card, and an image FIR filter and JPEG decoder are mapped onto the models. The experiment results show that when multiple cores are used for coprocessor, high kernel level speedup can be achieved. We also estimated that processor with dual-core coprocessor can achieve 1.2 to 1.66 of speedup at application level for JPEG decoding by analyzing algorithmic complexity of kernels in JPEG decoder.